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8-bit AVR Microcontroller with 1К Byte Flash ATtiny15L

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If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSR is set). Table 20. 0 Single-ended Input 000 ADC0 (PB5) 001 ADC1 (PB2) 010 ADC2 (PB3) 011 ADC3 (PB4) Positive Differential Input Negative Differential Input Gain N/A 100 (1) 101 (1) ADC2 (PB3) ADC2 (PB3) 1x ADC2 (PB3) ADC2 (PB3) 20x 110 ADC2 (PB3) ADC3 (PB4) 1x 111 ADC2 (PB3) ADC3 (PB4) 20x N/A Note: The ADC Control and Status Register – ADCSR 1. For offset calibration only.

High-voltage Serial Programming Waveforms SERIAL DATA INPUT PB0 MSB SERIAL INSTR. INPUT PB1 MSB SERIAL DATA OUTPUT PB2 56 LSB MSB 0 INTERNAL CK SERIAL CLOCK INPUT PB3 LSB LSB 1 2 3 4 5 6 7 8 9 10 16x ATtiny15L 1187F–AVR–06/05 ATtiny15L Table 25. 3 until PB2 goes high for the Chip Erase cycle to finish. 2 for a new 256 byte page. 3 for each new address. 3 until PB2 goes high. 1, Instr. 3 for each new address. 3 until PB2 goes high. 1, Instr. 3 for each new address. 3 for each new address. 2 for each new address.

Three data memory address locations are allocated for Port B, one each for the Data Register – PORTB, $18, Data Direction Register – DDRB, $17, and the Port B Input Pins – PINB, $16. The Port B Input Pins address is read-only, while the Data Register and the Data Direction Register are read/write. 0 have special functions as described in the section “Pin Descriptions” on page 4. If PB5 is not configured as External Reset, it is input with no pull-up or as an open-drain output. All I/O pins have individually selectable pull-ups, which can be overridden with pull-up disable.

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